mirror of https://github.com/YosysHQ/yosys.git
7 lines
243 B
Systemverilog
7 lines
243 B
Systemverilog
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module top_properties (input logic clock, read, write, ready);
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a_rw: assert property ( @(posedge clock) !(read && write) );
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a_wr: assert property ( @(posedge clock) write |-> ready );
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endmodule
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bind top top_properties properties_inst (.*);
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