mirror of https://github.com/YosysHQ/yosys.git
11 lines
375 B
Systemverilog
11 lines
375 B
Systemverilog
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module top (input logic clk, input logic selA, selB, QA, QB, output logic Q);
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always @(posedge clk) begin
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if (selA) Q <= QA;
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if (selB) Q <= QB;
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end
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check_selA: assert property ( @(posedge clk) selA|=> Q == $past(QA) );
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check_selB: assert property ( @(posedge clk) selB|=> Q == $past(QB) );
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assume_not_11: assume property ( @(posedge clk) !(selA& selB) );
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endmodule
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