mirror of https://github.com/YosysHQ/yosys.git
15 lines
384 B
Verilog
15 lines
384 B
Verilog
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module $__PP3_DFFEPC_SYNCONLY (
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output Q,
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input D,
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input CLK,
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input EN,
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);
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// For some reason ABC9 adds init attributes to wires even though they were removed before mapping.
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// As a workaround, remove any init attributes that get reintroduced.
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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dffepc _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CLK(CLK), .EN(EN), .PRE(1'b0), .CLR(1'b0));
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endmodule
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