mirror of https://github.com/YosysHQ/yosys.git
31 lines
663 B
Verilog
31 lines
663 B
Verilog
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module $__NX_RFB_L_ (
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input PORT_W_CLK,
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input PORT_W_WR_EN,
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input [5:0] PORT_W_ADDR,
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input [15:0] PORT_W_WR_DATA,
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input PORT_R_CLK,
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input PORT_R_RD_EN,
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input [5:0] PORT_R_ADDR,
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output [15:0] PORT_R_RD_DATA,
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);
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parameter INIT = 1152'bx;
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parameter PORT_W_CLK_POL = 1'b1;
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parameter PORT_R_CLK_POL = 1'b1;
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NX_RFB_L_WRAP #(
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.mode(0),
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.mem_ctxt(INIT),
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.rck_edge(~PORT_R_CLK_POL),
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.wck_edge(~PORT_W_CLK_POL)
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) _TECHMAP_REPLACE_ (
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.RCK(PORT_R_CLK),
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.WCK(PORT_W_CLK),
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.I(PORT_W_WR_DATA),
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.RA(PORT_R_ADDR),
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.WA(PORT_W_ADDR),
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.RE(PORT_R_RD_EN),
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.WE(PORT_W_WR_EN),
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.O(PORT_R_RD_DATA)
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);
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endmodule
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