mirror of https://github.com/YosysHQ/yosys.git
12 lines
126 B
Coq
12 lines
126 B
Coq
|
module simple_if();
|
||
|
|
|
||
|
|
reg latch;
|
||
|
|
wire enable,din;
|
||
|
|
|
||
|
|
always @ (enable or din)
|
||
|
|
if (enable) begin
|
||
|
|
latch <= din;
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|