mirror of https://github.com/YosysHQ/yosys.git
18 lines
274 B
Plaintext
18 lines
274 B
Plaintext
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read_verilog <<EOT
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module uut(
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input [15:0] a, b,
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input sel,
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output [15:0] res,
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);
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assign res = {sel ? a + b : a - b};
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endmodule
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EOT
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copy uut after
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opt_share after
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clean
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show -format dot -prefix opt_share_full -notitle -color cornflowerblue uut
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