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yosys/tests/arch/intel_alm/counter.ys

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synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
intel_alm: Add global buffer insertion Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 08:34:48 -05:00
equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
intel_alm: Fix illegal carry chains Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 08:40:37 -05:00
select -assert-count 1 t:MISTRAL_NOT
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-count 8 t:MISTRAL_FF
intel_alm: add Cyclone 10 GX tests
2020-07-05 12:53:14 -05:00
select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
design -reset
read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
intel_alm: Add global buffer insertion Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 08:34:48 -05:00
equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
intel_alm: add Cyclone 10 GX tests
2020-07-05 12:53:14 -05:00
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
intel_alm: Fix illegal carry chains Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 08:40:37 -05:00
select -assert-count 1 t:MISTRAL_NOT
intel_alm: add Cyclone 10 GX tests
2020-07-05 12:53:14 -05:00
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-count 8 t:MISTRAL_FF
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 04:19:00 -06:00
select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D