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8c3de1d4bd
yosys
/
tests
/
arch
/
common
/
mul.v
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Add tests for ECP5 architecture
2019-09-03 03:53:37 -05:00
module
top
(
Unify verilog style
2019-10-18 05:50:24 -05:00
input
[
5
:
0
]
x
,
input
[
5
:
0
]
y
,
Add tests for ECP5 architecture
2019-09-03 03:53:37 -05:00
Unify verilog style
2019-10-18 05:50:24 -05:00
output
[
11
:
0
]
A
,
)
;
assign
A
=
x
*
y
;
Add tests for ECP5 architecture
2019-09-03 03:53:37 -05:00
endmodule