mirror of https://github.com/YosysHQ/yosys.git
25 lines
476 B
Verilog
25 lines
476 B
Verilog
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module \$add (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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generate
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if ((A_WIDTH == 32) && (B_WIDTH == 32))
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begin
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wire [16:0] S1 = A[15:0] + B[15:0];
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wire [15:0] S2 = A[31:16] + B[31:16] + S1[16];
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assign Y = {S2[15:0], S1[15:0]};
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end
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else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule
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