mirror of https://github.com/YosysHQ/yosys.git
8 lines
134 B
Verilog
8 lines
134 B
Verilog
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module test(input D, C, R, output reg Q);
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always @(posedge C, posedge R)
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if (R)
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Q <= 0;
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else
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Q <= D;
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endmodule
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