mirror of https://github.com/YosysHQ/yosys.git
11 lines
168 B
Verilog
11 lines
168 B
Verilog
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module test(input clk, a, b, c,
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output reg y);
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reg [2:0] q1, q2;
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always @(posedge clk) begin
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q1 <= { a, b, c };
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q2 <= q1;
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y <= ^q2;
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end
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endmodule
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