mirror of https://github.com/YosysHQ/yosys.git
6 lines
102 B
Verilog
6 lines
102 B
Verilog
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module test (A, B, X, Y);
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input [7:0] A, B;
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output [7:0] X = A + B;
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output [7:0] Y = A + A;
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endmodule
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