mirror of https://github.com/YosysHQ/yosys.git
19 lines
772 B
Plaintext
19 lines
772 B
Plaintext
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read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev
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async2sync
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 6 t:MISTRAL_FF
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select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
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select -assert-count 5 t:MISTRAL_ALUT5
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select -assert-count 1 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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