mirror of https://github.com/YosysHQ/yosys.git
288 lines
8.2 KiB
Verilog
288 lines
8.2 KiB
Verilog
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`timescale 1ns / 1ps
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module testbench;
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parameter integer AREG = 1;
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parameter integer BREG = 1;
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parameter integer CREG = 1;
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parameter integer MREG = 1;
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parameter integer PREG = 1;
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parameter integer CARRYINREG = 1;
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parameter integer CARRYINSELREG = 1;
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parameter integer OPMODEREG = 1;
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parameter integer SUBTRACTREG = 1;
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parameter B_INPUT = "DIRECT";
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parameter LEGACY_MODE = "NONE";
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reg CLK;
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reg CEA, CEB, CEC, CEM, CEP, CECARRYIN, CECINSUB, CECTRL;
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reg RSTA, RSTB, RSTC, RSTM, RSTP, RSTCARRYIN, RSTCTRL;
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reg [17:0] A;
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reg [17:0] B;
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reg [47:0] C;
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reg [17:0] BCIN;
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reg [47:0] PCIN;
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reg CARRYIN;
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reg [6:0] OPMODE;
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reg SUBTRACT;
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reg [1:0] CARRYINSEL;
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output [47:0] P, REF_P;
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output [17:0] BCOUT, REF_BCOUT;
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output [47:0] PCOUT, REF_PCOUT;
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integer errcount = 0;
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reg ERROR_FLAG = 0;
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task clkcycle;
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begin
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#5;
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CLK = ~CLK;
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#10;
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CLK = ~CLK;
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#2;
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ERROR_FLAG = 0;
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if (REF_BCOUT !== BCOUT) begin
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$display("ERROR at %1t: REF_BCOUT=%b UUT_BCOUT=%b DIFF=%b", $time, REF_BCOUT, BCOUT, REF_BCOUT ^ BCOUT);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_P !== P) begin
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$display("ERROR at %1t: REF_P=%b UUT_P=%b DIFF=%b", $time, REF_P, P, REF_P ^ P);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_PCOUT !== PCOUT) begin
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$display("ERROR at %1t: REF_PCOUT=%b UUT_PCOUT=%b DIFF=%b", $time, REF_PCOUT, PCOUT, REF_PCOUT ^ PCOUT);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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#3;
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end
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endtask
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reg config_valid = 0;
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task drc;
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begin
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config_valid = 1;
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if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0;
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if (OPMODE[1:0] == 2'b00 && CARRYINSEL == 2'b10) config_valid = 0;
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if (OPMODE[1:0] == 2'b10 && CARRYINSEL == 2'b10) config_valid = 0;
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if (OPMODE[1:0] == 2'b00 && CARRYINSEL == 2'b11) config_valid = 0;
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if (OPMODE[1:0] == 2'b10 && CARRYINSEL == 2'b11) config_valid = 0;
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if (OPMODE[3:2] == 2'b10) config_valid = 0;
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if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0;
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if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0;
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if (OPMODE[6:4] == 3'b100) config_valid = 0;
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if (OPMODE[6:4] == 3'b111) config_valid = 0;
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if (OPMODE[6:4] == 3'b000 && CARRYINSEL == 2'b01) config_valid = 0;
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if (OPMODE[6:4] == 3'b011 && CARRYINSEL == 2'b01) config_valid = 0;
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// Xilinx models consider these combinations invalid for an unknown reason.
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if (CARRYINSEL == 2'b01 && OPMODE[3:2] == 2'b00) config_valid = 0;
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if (CARRYINSEL == 2'b10 && OPMODE == 7'b0000011) config_valid = 0;
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if (CARRYINSEL == 2'b10 && OPMODE == 7'b0000101) config_valid = 0;
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if (CARRYINSEL == 2'b10 && OPMODE == 7'b0100011) config_valid = 0;
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if (CARRYINSEL == 2'b10 && OPMODE == 7'b0111111) config_valid = 0;
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if (CARRYINSEL == 2'b10 && OPMODE == 7'b1100011) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b0000011) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b0000101) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b0011111) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b0010011) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b0100011) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b0100101) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b0101111) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b0110011) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b0111111) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b1010011) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b1011111) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b1100011) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b1100101) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE == 7'b1101111) config_valid = 0;
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if (CARRYINSEL == 2'b10 && OPMODE[3:0] == 4'b0101 && MREG == 1) config_valid = 0;
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if (CARRYINSEL == 2'b11 && OPMODE[3:0] == 4'b0101 && MREG == 0) config_valid = 0;
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end
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endtask
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initial begin
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$dumpfile("test_dsp48_model.vcd");
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$dumpvars(0, testbench);
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#2;
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CLK = 1'b0;
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{CEA, CEB, CEC, CEM, CEP, CECARRYIN, CECINSUB, CECTRL} = 8'b11111111;
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{A, B, C, PCIN, OPMODE, SUBTRACT, CARRYIN, CARRYINSEL} = 0;
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{RSTA, RSTB, RSTC, RSTM, RSTP, RSTCARRYIN, RSTCTRL} = 7'b1111111;
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repeat (10) begin
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#10;
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CLK = 1'b1;
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#10;
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CLK = 1'b0;
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#10;
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CLK = 1'b1;
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#10;
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CLK = 1'b0;
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end
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{RSTA, RSTB, RSTC, RSTM, RSTP, RSTCARRYIN, RSTCTRL} = 0;
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repeat (100000) begin
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clkcycle;
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config_valid = 0;
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while (!config_valid) begin
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A = $urandom;
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B = $urandom;
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C = {$urandom, $urandom};
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BCIN = $urandom;
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PCIN = {$urandom, $urandom};
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{CEA, CEB, CEC, CEM, CEP, CECARRYIN, CECINSUB, CECTRL} = $urandom | $urandom | $urandom;
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{RSTA, RSTB, RSTC, RSTM, RSTP, RSTCARRYIN, RSTCTRL} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
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{CARRYIN, CARRYINSEL, OPMODE, SUBTRACT} = $urandom;
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drc;
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end
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end
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if (errcount == 0) begin
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$display("All tests passed.");
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$finish;
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end else begin
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$display("Caught %1d errors.", errcount);
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$stop;
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end
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end
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DSP48 #(
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.AREG (AREG),
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.BREG (BREG),
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.CREG (CREG),
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.MREG (MREG),
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.PREG (PREG),
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.CARRYINREG (CARRYINREG),
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.CARRYINSELREG (CARRYINSELREG),
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.OPMODEREG (OPMODEREG),
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.SUBTRACTREG (SUBTRACTREG),
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.B_INPUT (B_INPUT),
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.LEGACY_MODE (LEGACY_MODE)
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) ref (
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.A (A),
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.B (B),
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.C (C),
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.BCIN (BCIN),
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.PCIN (PCIN),
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.CARRYIN (CARRYIN),
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.OPMODE (OPMODE),
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.SUBTRACT (SUBTRACT),
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.CARRYINSEL (CARRYINSEL),
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.BCOUT (REF_BCOUT),
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.P (REF_P),
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.PCOUT (REF_PCOUT),
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.CEA (CEA),
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.CEB (CEB),
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.CEC (CEC),
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.CEM (CEM),
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.CEP (CEP),
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.CECARRYIN (CECARRYIN),
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.CECINSUB (CECINSUB),
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.CECTRL (CECTRL),
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.CLK (CLK),
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.RSTA (RSTA),
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.RSTB (RSTB),
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.RSTC (RSTC),
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.RSTM (RSTM),
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.RSTP (RSTP),
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.RSTCARRYIN (RSTCARRYIN),
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.RSTCTRL (RSTCTRL)
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);
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DSP48_UUT #(
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.AREG (AREG),
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.BREG (BREG),
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.CREG (CREG),
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.MREG (MREG),
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.PREG (PREG),
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.CARRYINREG (CARRYINREG),
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.CARRYINSELREG (CARRYINSELREG),
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.OPMODEREG (OPMODEREG),
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.SUBTRACTREG (SUBTRACTREG),
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.B_INPUT (B_INPUT),
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.LEGACY_MODE (LEGACY_MODE)
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) uut (
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.A (A),
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.B (B),
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.C (C),
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.BCIN (BCIN),
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.PCIN (PCIN),
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.CARRYIN (CARRYIN),
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.OPMODE (OPMODE),
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.SUBTRACT (SUBTRACT),
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.CARRYINSEL (CARRYINSEL),
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.BCOUT (BCOUT),
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.P (P),
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.PCOUT (PCOUT),
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.CEA (CEA),
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.CEB (CEB),
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.CEC (CEC),
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.CEM (CEM),
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.CEP (CEP),
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.CECARRYIN (CECARRYIN),
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.CECINSUB (CECINSUB),
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.CECTRL (CECTRL),
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.CLK (CLK),
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.RSTA (RSTA),
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.RSTB (RSTB),
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.RSTC (RSTC),
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.RSTM (RSTM),
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.RSTP (RSTP),
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.RSTCARRYIN (RSTCARRYIN),
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.RSTCTRL (RSTCTRL)
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);
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endmodule
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module mult_noreg;
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testbench #(
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.AREG (0),
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.BREG (0),
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.CREG (0),
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.MREG (0),
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.PREG (0),
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.CARRYINREG (0),
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.CARRYINSELREG (0),
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.OPMODEREG (0),
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.SUBTRACTREG (0),
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.B_INPUT ("DIRECT")
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) testbench ();
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endmodule
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module mult_allreg;
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testbench #(
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.AREG (1),
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.BREG (1),
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.CREG (1),
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.MREG (1),
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.PREG (1),
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.CARRYINREG (1),
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.CARRYINSELREG (1),
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.OPMODEREG (1),
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.SUBTRACTREG (1),
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.B_INPUT ("CASCADE")
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) testbench ();
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endmodule
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module mult_inreg;
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testbench #(
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.AREG (1),
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.BREG (1),
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.CREG (1),
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.MREG (0),
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.PREG (0),
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.CARRYINREG (1),
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.CARRYINSELREG (0),
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.OPMODEREG (0),
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.SUBTRACTREG (0),
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.B_INPUT ("DIRECT")
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) testbench ();
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endmodule
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