mirror of https://github.com/YosysHQ/yosys.git
100 lines
2.5 KiB
Plaintext
100 lines
2.5 KiB
Plaintext
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r -chparam A_WIDTH 4
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 1 t:BUFG
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select -assert-count 8 t:FDRE
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select -assert-count 8 t:RAM16X1D
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select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r -chparam A_WIDTH 5
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 1 t:BUFG
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select -assert-count 8 t:FDRE
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select -assert-count 8 t:RAM32X1D
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select -assert-none t:BUFG t:FDRE t:RAM32X1D %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 1 t:BUFG
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select -assert-count 8 t:FDRE
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select -assert-count 8 t:RAM64X1D
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select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w3r
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proc
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memory -nomap
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synth_xilinx
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w3r
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select -assert-count 1 t:BUFG
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select -assert-count 24 t:FDRE
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select -assert-count 4 t:RAM32M
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select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w3r -chparam A_WIDTH 6
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proc
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memory -nomap
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synth_xilinx
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w3r
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select -assert-count 1 t:BUFG
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select -assert-count 24 t:FDRE
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select -assert-count 8 t:RAM64M
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select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
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