yosys/tests/verilog/unnamed_block.ys

read_verilog <<EOT
module top;
    initial begin : blk
        integer x;
    end
endmodule
EOT

delete

read_verilog -sv <<EOT
module top;
    initial begin
        integer x;
    end
endmodule
EOT

delete

logger -expect error "Local declaration in unnamed block is only supported in SystemVerilog mode!" 1
read_verilog <<EOT
module top;
    initial begin
        integer x;
    end
endmodule
EOT
verilog: significant block scoping improvements This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493 2021-01-27 12:30:22 -06:00			`read_verilog <<EOT`
			`module top;`
			`initial begin : blk`
			`integer x;`
			`end`
			`endmodule`
			`EOT`

			`delete`

			`read_verilog -sv <<EOT`
			`module top;`
			`initial begin`
			`integer x;`
			`end`
			`endmodule`
			`EOT`

			`delete`

			`logger -expect error "Local declaration in unnamed block is only supported in SystemVerilog mode!" 1`
			`read_verilog <<EOT`
			`module top;`
			`initial begin`
			`integer x;`
			`end`
			`endmodule`
			`EOT`