yosys/tests/verilog/struct_access.ys

mirror of https://github.com/YosysHQ/yosys.git
read_verilog -formal -sv struct_access.sv
proc
opt -full
sat -verify -seq 1 -prove-asserts -show-all
sv: fix two struct access bugs - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions) 2021-06-22 09:39:57 -05:00			`read_verilog -formal -sv struct_access.sv`
			`proc`
			`opt -full`
			`sat -verify -seq 1 -prove-asserts -show-all`