yosys/tests/verilog/genvar_loop_decl_3.ys

read_verilog -sv genvar_loop_decl_3.sv
proc
equiv_make gold gate equiv
equiv_simple
equiv_status -assert
sv: support declaration in generate for initialization This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected. 2021-08-31 12:45:02 -05:00			`read_verilog -sv genvar_loop_decl_3.sv`
			`proc`
			`equiv_make gold gate equiv`
			`equiv_simple`
			`equiv_status -assert`