mirror of https://github.com/YosysHQ/yosys.git
19 lines
585 B
Plaintext
19 lines
585 B
Plaintext
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read_verilog ../common/blockram.v
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design -save read
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# Check that we use the right dual and single clock variants
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp
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synth_nexus -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 1 t:PDPSC16K
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select -assert-none t:PDPSC16K t:INV t:IB t:OB t:VLO t:VHI %% t:* %D
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design -reset
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read_verilog blockram_dc.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp_dc
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synth_nexus -top sync_ram_sdp_dc
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cd sync_ram_sdp_dc
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select -assert-count 1 t:PDP16K
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select -assert-none t:PDP16K t:INV t:IB t:OB t:VLO t:VHI %% t:* %D
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