yosys/manual/PRESENTATION_ExAdv/sym_mul_test.v

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2014-02-16 07:32:56 -06:00
module test(A, B, C, Y1, Y2);
input [7:0] A, B, C;
output [7:0] Y1 = A * B;
output [15:0] Y2 = A * C;
endmodule