mirror of https://github.com/YosysHQ/yosys.git
63 lines
1.2 KiB
Verilog
63 lines
1.2 KiB
Verilog
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module LUT4 #(
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parameter [15:0] INIT = 0
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) (
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input A, B, C, D,
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output F
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);
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wire [3:0] I;
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wire [3:0] I_pd;
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genvar ii;
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generate
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for (ii = 0; ii < 4; ii = ii + 1'b1)
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assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii];
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endgenerate
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assign I = {D, C, B, A};
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assign F = INIT[I_pd];
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endmodule
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module FACADE_FF #(
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parameter GSR = "ENABLED",
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parameter CEMUX = "1",
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parameter CLKMUX = "0",
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parameter LSRMUX = "LSR",
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parameter LSRONMUX = "LSRMUX",
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parameter SRMODE = "LSR_OVER_CE",
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parameter REGSET = "SET"
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) (
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input CLK, D, LSR, CE,
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output reg Q
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);
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wire muxce;
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generate
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case (CEMUX)
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"1": assign muxce = 1'b1;
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"0": assign muxce = 1'b0;
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"INV": assign muxce = ~CE;
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default: assign muxce = CE;
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endcase
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endgenerate
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wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
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wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
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assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
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generate
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if (SRMODE == "ASYNC") begin
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always @(posedge muxclk, posedge muxlsr)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end else begin
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always @(posedge muxclk)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end
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endgenerate
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endmodule
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