yosys/tests/errors/syntax_err09.v

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module a(input wire x = 1'b0);
endmodule
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages. 2018-10-24 18:37:56 -05:00			`module a(input wire x = 1'b0);`
			`endmodule`