mirror of https://github.com/YosysHQ/yosys.git
17 lines
330 B
Verilog
17 lines
330 B
Verilog
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// expect-wr-ports 1
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// expect-rd-ports 1
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// expect-no-rd-clk
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module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
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reg [7:0] bram[0:255];
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(* keep *) reg dummy;
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always @(posedge clk) begin
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rdata <= re ? (reset ? 8'b0 : bram[addr]) : rdata;
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if (we)
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bram[addr] <= wdata;
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end
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endmodule
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