mirror of https://github.com/YosysHQ/yosys.git
82 lines
1.2 KiB
Plaintext
82 lines
1.2 KiB
Plaintext
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read_verilog -specify <<EOT
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module buffer(input i, output o);
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specify
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(i => o) = 10;
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endspecify
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endmodule
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module top(input i);
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wire w;
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buffer b(.i(i), .o(w));
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endmodule
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EOT
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logger -expect warning "Critical-path does not terminate in a recognised endpoint\." 1
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sta
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design -reset
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read_verilog -specify <<EOT
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module top(input i, output o, p);
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assign o = i;
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endmodule
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EOT
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logger -expect log "No timing paths found\." 1
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sta
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design -reset
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read_verilog -specify <<EOT
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module buffer(input i, output o);
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specify
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(i => o) = 10;
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endspecify
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endmodule
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module top(input i, output o, p);
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buffer b(.i(i), .o(o));
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endmodule
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EOT
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sta
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design -reset
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read_verilog -specify <<EOT
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module buffer(input i, output o);
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specify
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(i => o) = 10;
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endspecify
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endmodule
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module top(input i, output o, p);
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buffer b(.i(i), .o(o));
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const0 c(.o(p));
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endmodule
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EOT
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logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1
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sta
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design -reset
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read_verilog -specify <<EOT
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module buffer(input i, output o);
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specify
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(i => o) = 10;
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endspecify
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endmodule
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module const0(output o);
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endmodule
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module top(input i, output o, p);
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buffer b(.i(i), .o(o));
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const0 c(.o(p));
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endmodule
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EOT
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sta
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logger -expect-no-warnings
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