mirror of https://github.com/YosysHQ/yosys.git
10 lines
126 B
Coq
10 lines
126 B
Coq
|
module tri_buf (a,b,enable);
|
||
|
|
input a;
|
||
|
|
output b;
|
||
|
|
input enable;
|
||
|
|
wire b;
|
||
|
|
|
||
|
|
assign b = (enable) ? a : 1'bz;
|
||
|
|
|
||
|
|
endmodule
|