mirror of https://github.com/YosysHQ/yosys.git
96 lines
2.2 KiB
Bash
96 lines
2.2 KiB
Bash
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#!/bin/bash
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set -ex
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SZA=$(( 3 + $RANDOM % 13 ))
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SZB=$(( 3 + $RANDOM % 13 ))
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SZO=$(( 3 + $RANDOM % 29 ))
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C0=clk$(( $RANDOM & 1))
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C1=clk$(( $RANDOM & 1))
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C2=clk$(( $RANDOM & 1))
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C3=clk$(( $RANDOM & 1))
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E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
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E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
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E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
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E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
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SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P )
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RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" )
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RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )"
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cat > test_dsp_map_top.v << EOT
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module top (
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input clk0, clk1, reset,
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input [$SZA:0] A,
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input [$SZB:0] B,
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output [$SZO:0] O
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);
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reg [15:0] AA, BB;
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reg [31:0] P, S;
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always @($E0 $C0) AA <= A;
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always @($E1 $C1) BB <= B;
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always @($E2 $C2) P <= AA * BB;
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always @($E3 $C3) S <= $RC ? $RV : S + P;
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assign O = $SP;
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endmodule
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EOT
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cat > test_dsp_map_tb.v << EOT
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\`timescale 1ns / 1ps
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module testbench;
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reg clk1, clk0, reset;
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reg [$SZA:0] A;
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reg [$SZB:0] B;
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wire [$SZO:0] O_top, O_syn;
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top top_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_top));
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syn syn_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_syn));
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initial begin
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#2;
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clk0 = 0;
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clk1 = 0;
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reset = 1;
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A = 0;
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B = 0;
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repeat (3) begin
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#2; clk0 = ~clk0;
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#2; clk0 = ~clk0;
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#2; clk1 = ~clk1;
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#2; clk1 = ~clk1;
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end
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repeat (100) begin
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#2;
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A = \$urandom;
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B = \$urandom;
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reset = \$urandom & \$urandom & \$urandom & \$urandom;
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if (\$urandom & 1) begin
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#2; clk0 = ~clk0;
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#2; clk0 = ~clk0;
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end else begin
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#2; clk1 = ~clk1;
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#2; clk1 = ~clk1;
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end
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#2;
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if (O_top !== O_syn) begin
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\$display("ERROR: O_top=%b O_syn=%b", O_top, O_syn);
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\$stop;
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end
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\$display("OK O_top=O_syn=%b", O_top);
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end
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\$finish;
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end
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endmodule
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EOT
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../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v'
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iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v
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vvp -N test_dsp_map
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