mirror of https://github.com/YosysHQ/yosys.git
9 lines
117 B
Verilog
9 lines
117 B
Verilog
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module tb;
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reg clk = 0;
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top uut (.clk(clk));
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always #1 clk <= ~clk;
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initial #20 $finish;
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endmodule
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