mirror of https://github.com/YosysHQ/yosys.git
51 lines
1.7 KiB
Plaintext
51 lines
1.7 KiB
Plaintext
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read_verilog ../common/mux.v
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design -save read
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hierarchy -top mux2
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 3 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top mux4
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 2 t:LUT4
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select -assert-count 6 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top mux8
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 5 t:LUT4
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select -assert-count 11 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top mux16
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 9 t:LUT4
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select -assert-count 3 t:LUT3
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select -assert-count 20 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT4 t:LUT3 t:IBUF t:OBUF %% t:* %D
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