mirror of https://github.com/YosysHQ/yosys.git
56 lines
1.3 KiB
Verilog
56 lines
1.3 KiB
Verilog
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`ifdef cyclonev
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`define SYNCPATH 262
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`define SYNCSETUP 522
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`define COMBPATH 0
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`endif
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`ifdef cyclone10gx
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`define SYNCPATH 219
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`define SYNCSETUP 268
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`define COMBPATH 0
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`endif
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// fallback for when a family isn't detected (e.g. when techmapping for equivalence)
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`ifndef SYNCPATH
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`define SYNCPATH 0
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`define SYNCSETUP 0
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`define COMBPATH 0
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`endif
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// This is a purely-synchronous flop, that ABC9 can use for sequential synthesis.
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(* abc9_flop, lib_whitebox *)
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module MISTRAL_FF_SYNCONLY(
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input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA,
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output reg Q
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);
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specify
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if (ENA) (posedge CLK => (Q : DATAIN)) = `SYNCPATH;
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if (ENA) (posedge CLK => (Q : SCLR)) = `SYNCPATH;
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if (ENA) (posedge CLK => (Q : SLOAD)) = `SYNCPATH;
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if (ENA) (posedge CLK => (Q : SDATA)) = `SYNCPATH;
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$setup(DATAIN, posedge CLK, `SYNCSETUP);
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$setup(ENA, posedge CLK, `SYNCSETUP);
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$setup(SCLR, posedge CLK, `SYNCSETUP);
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$setup(SLOAD, posedge CLK, `SYNCSETUP);
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$setup(SDATA, posedge CLK, `SYNCSETUP);
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endspecify
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initial begin
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// Altera flops initialise to zero.
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Q = 0;
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end
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always @(posedge CLK) begin
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// Clock-enable
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if (ENA) begin
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// Synchronous clear
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if (SCLR) Q <= 0;
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// Synchronous load
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else if (SLOAD) Q <= SDATA;
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else Q <= DATAIN;
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end
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end
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endmodule
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