mirror of https://github.com/YosysHQ/yosys.git
29 lines
460 B
Plaintext
29 lines
460 B
Plaintext
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read_verilog <<EOT
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module top;
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task foo;
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endtask
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always @*
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(* foo *) foo;
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initial
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if (0) $info("bar");
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endmodule
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EOT
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# Since task enables are not an RTLIL object,
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# any attributes on their AST get dropped
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select -assert-none a:* a:src %d
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logger -expect error "syntax error, unexpected ATTR_BEGIN" 1
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design -reset
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read_verilog <<EOT
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module top;
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task foo;
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endtask
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always @*
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foo (* foo *);
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endmodule
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EOT
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