mirror of https://github.com/YosysHQ/yosys.git
54 lines
1.8 KiB
ReStructuredText
54 lines
1.8 KiB
ReStructuredText
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.. role:: verilog(code)
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:language: Verilog
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Combinatorial cells (combined)
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------------------------------
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These cells combine two or more combinatorial cells (simple) into a single cell.
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.. table:: Cell types for gate level combinatorial cells (combined)
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======================================= =============
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Verilog Cell Type
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======================================= =============
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:verilog:`Y = A & ~B` `$_ANDNOT_`
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:verilog:`Y = A | ~B` `$_ORNOT_`
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:verilog:`Y = ~((A & B) | C)` `$_AOI3_`
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:verilog:`Y = ~((A | B) & C)` `$_OAI3_`
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:verilog:`Y = ~((A & B) | (C & D))` `$_AOI4_`
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:verilog:`Y = ~((A | B) & (C | D))` `$_OAI4_`
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:verilog:`Y = ~(S ? B : A)` `$_NMUX_`
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(see below) `$_MUX4_`
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(see below) `$_MUX8_`
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(see below) `$_MUX16_`
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======================================= =============
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The `$_MUX4_`, `$_MUX8_` and `$_MUX16_` cells are used to model wide muxes, and
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correspond to the following Verilog code:
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.. code-block:: verilog
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:force:
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// $_MUX4_
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assign Y = T ? (S ? D : C) :
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(S ? B : A);
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// $_MUX8_
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assign Y = U ? T ? (S ? H : G) :
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(S ? F : E) :
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T ? (S ? D : C) :
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(S ? B : A);
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// $_MUX16_
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assign Y = V ? U ? T ? (S ? P : O) :
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(S ? N : M) :
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T ? (S ? L : K) :
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(S ? J : I) :
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U ? T ? (S ? H : G) :
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(S ? F : E) :
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T ? (S ? D : C) :
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(S ? B : A);
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.. autocellgroup:: comb_combined
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:members:
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:source:
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:linenos:
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