mirror of https://github.com/YosysHQ/yosys.git
15 lines
155 B
Plaintext
15 lines
155 B
Plaintext
|
read_rtlil << EOT
|
||
|
|
|
||
|
|
module \top
|
||
|
|
wire output 1 \a
|
||
|
|
wire width 0 $dummy
|
||
|
|
cell \abc \abc
|
||
|
|
connect \a \a
|
||
|
|
connect \b $dummy
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
EOT
|
||
|
|
|
||
|
|
opt_clean
|