mirror of https://github.com/YosysHQ/yosys.git
11 lines
215 B
Verilog
11 lines
215 B
Verilog
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(* blackbox *)
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module NX_GCK_U(SI1, SI2, CMD, SO);
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input CMD;
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input SI1;
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input SI2;
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output SO;
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parameter inv_in = 1'b0;
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parameter inv_out = 1'b0;
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parameter std_mode = "BYPASS";
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endmodule
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