mirror of https://github.com/YosysHQ/yosys.git
18 lines
514 B
Plaintext
18 lines
514 B
Plaintext
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# read test design
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read_verilog ../PRESENTATION_ExSyn/techmap_01.v
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hierarchy -top test
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# create two version of the design: test_orig and test_mapped
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copy test test_orig
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rename test test_mapped
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# apply the techmap only to test_mapped
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techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped
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# create a miter circuit to test equivialence
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miter -equiv -make_assert -make_outputs test_orig test_mapped miter
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flatten miter
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# run equivialence check
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sat -verify -prove-asserts -show-inputs -show-outputs miter
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