mirror of https://github.com/YosysHQ/yosys.git
8 lines
137 B
Verilog
8 lines
137 B
Verilog
|
module top;
|
||
|
|
parameter STR = "something interesting";
|
||
|
|
initial begin
|
||
|
|
$display("A: %s", STR);
|
||
|
|
$display("B: %0s", STR);
|
||
|
|
end
|
||
|
|
endmodule
|