mirror of https://github.com/YosysHQ/yosys.git
20 lines
398 B
Verilog
20 lines
398 B
Verilog
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module top(
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input clk,
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input wire [1:0] sel,
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input wire [7:0] base,
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output reg [7:0] line
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);
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reg [0:7] mem [0:2];
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generate
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genvar i;
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for (i = 0; i < 4; i = i + 1) begin : gen
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always @(posedge clk)
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mem[i] <= i == 0 ? base : mem[i - 1] + 1;
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end
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endgenerate
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always @(posedge clk)
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line = mem[sel];
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endmodule
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