mirror of https://github.com/YosysHQ/yosys.git
68 lines
2.6 KiB
Plaintext
68 lines
2.6 KiB
Plaintext
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read_verilog ../common/adffs.v
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design -save read
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hierarchy -top adff
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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select -assert-count 1 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 1 t:inpad
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select -assert-count 1 t:outpad
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select -assert-count 2 t:ckpad
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select -assert-none t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
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design -load read
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hierarchy -top adffn
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT1
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select -assert-count 1 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 2 t:inpad
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select -assert-count 1 t:outpad
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select -assert-count 1 t:ckpad
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select -assert-none t:LUT1 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
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design -load read
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hierarchy -top dffs
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT2
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select -assert-count 1 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 3 t:inpad
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select -assert-count 1 t:outpad
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select -assert-count 1 t:ckpad
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select -assert-none t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
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design -load read
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hierarchy -top ndffnr
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT1
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select -assert-count 1 t:LUT2
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select -assert-count 1 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 4 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT1 t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad %% t:* %D
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