yosys/tests/errors/syntax_err02.v

mirror of https://github.com/YosysHQ/yosys.git
module a;
task to (
  input integer [3:0]x
);
endtask
endmodule
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages. 2018-10-24 18:37:56 -05:00			`module a;`
			`task to (`
			`input integer [3:0]x`
			`);`
			`endtask`
			`endmodule`