mirror of https://github.com/YosysHQ/yosys.git
10 lines
372 B
Plaintext
10 lines
372 B
Plaintext
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read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v;
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prep -top grom_computer;
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sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -a -n 80
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sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp
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sim -clock clk -r grom.fst -scope grom_computer -stop 100ns -sim-gold
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sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate -a
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