mirror of https://github.com/YosysHQ/yosys.git
26 lines
1007 B
Plaintext
26 lines
1007 B
Plaintext
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read_verilog macc.v
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proc
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design -save read
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hierarchy -top top
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equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:SB_MAC16
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select -assert-none t:SB_MAC16 %% t:* %D
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design -load read
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hierarchy -top top2
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#equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
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equiv_opt -run :prove -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
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clk2fflogic
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -set-init-zero -seq 4 -verify -prove-asserts -show-ports miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:SB_MAC16
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select -assert-none t:SB_MAC16 %% t:* %D
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