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7d8140ddea
yosys
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tests
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verilog
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func_tern_hint.ys
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verilog: fix width/sign detection for functions
2022-05-30 15:45:39 -05:00
read_verilog -sv func_tern_hint.sv
proc
opt
tests: Run async2sync before sat and/or sim to handle $check cells Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.
2024-01-22 10:44:05 -06:00
async2sync
verilog: fix width/sign detection for functions
2022-05-30 15:45:39 -05:00
sat -verify -seq 1 -prove-asserts -show-all