yosys/tests/verilog/unmatched_endif.ys

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logger -expect error "Found `endif outside of macro conditional branch!" 1
read_verilog <<EOT
module top;
`endif
endmodule
EOT
verilog: fix handling of nested ifdef directives - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else 2021-02-25 14:53:55 -06:00			logger -expect error "Found `endif outside of macro conditional branch!" 1
			`read_verilog <<EOT`
			`module top;`
			`endif
			`endmodule`
			`EOT`