yosys/tests/verilog/unmatched_else.ys

mirror of https://github.com/YosysHQ/yosys.git
logger -expect error "Found `else outside of macro conditional branch!" 1
read_verilog <<EOT
module top;
`else
endmodule
EOT
verilog: fix handling of nested ifdef directives - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else 2021-02-25 14:53:55 -06:00			logger -expect error "Found `else outside of macro conditional branch!" 1
			`read_verilog <<EOT`
			`module top;`
			`else
			`endmodule`
			`EOT`