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yosys/tests/sva/Makefile

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Improve SVA tests, add Makefile and scripts
2017-07-27 04:42:05 -05:00
Add simple VHDL+PSL example
2017-07-28 08:33:30 -05:00
TESTS = $(sort $(basename $(wildcard *.sv)) $(basename $(wildcard *.vhd)))
Improve SVA tests, add Makefile and scripts
2017-07-27 04:42:05 -05:00
all: $(addsuffix .ok,$(TESTS))
Add simple VHDL+PSL example
2017-07-28 08:33:30 -05:00
%.ok:
bash runtest.sh $@
Improve SVA tests, add Makefile and scripts
2017-07-27 04:42:05 -05:00
clean:
Add simple VHDL+PSL example
2017-07-28 08:33:30 -05:00
rm -rf $(addsuffix .ok,$(TESTS)) $(addsuffix .sby,$(TESTS)) $(TESTS)
Improve SVA tests, add Makefile and scripts
2017-07-27 04:42:05 -05:00
rm -rf $(addsuffix _pass.sby,$(TESTS)) $(addsuffix _pass,$(TESTS))
rm -rf $(addsuffix _fail.sby,$(TESTS)) $(addsuffix _fail,$(TESTS))
verific: Improve logic generated for SVA value change expressions The previously generated logic assumed an unconstrained past value in the initial state and did not handle 'x values. While the current formal verification flow uses 2-valued logic, SVA value change expressions require a past value of 'x during the initial state to behave in the expected way (i.e. to consider both an initial 0 and an initial 1 as $changed and an initial 1 as $rose and an initial 0 as $fell). This patch now generates logic that at the same time a) provides the expected behavior in a 2-valued logic setting, not depending on any dont-care optimizations, and b) properly handles 'x values in yosys simulation
2022-05-09 08:04:01 -05:00
rm -rf $(addsuffix .fst,$(TESTS))
Improve SVA tests, add Makefile and scripts
2017-07-27 04:42:05 -05:00