mirror of https://github.com/YosysHQ/yosys.git
47 lines
983 B
Verilog
47 lines
983 B
Verilog
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// expect-wr-ports 1
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// expect-rd-ports 4
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// expect-rd-wide-continuation 4'1110
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// expect-rd-srst-val 32'10000111011001010100001100100001
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// expect-rd-init-val 32'10101011110011011110111110101011
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// In this testcase, the byte-wide read ports are merged into a single
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// word-wide port despite mismatched transparency, with soft transparency
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// logic inserted on half the port to preserve the semantics.
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module test(
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input clk,
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input re, rr,
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input we,
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input [5:0] ra,
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input [7:0] wa,
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input [7:0] wd,
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output reg [31:0] rd
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);
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reg [7:0] mem[0:255];
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initial rd = 32'habcdefab;
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always @(posedge clk) begin
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if (rr) begin
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rd <= 32'h87654321;
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end else if (re) begin
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rd[7:0] <= mem[{ra, 2'b00}];
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rd[15:8] <= mem[{ra, 2'b01}];
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rd[23:16] <= mem[{ra, 2'b10}];
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rd[31:24] <= mem[{ra, 2'b11}];
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if (we && wa == {ra, 2'b00})
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rd [7:0] <= wd;
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if (we && wa == {ra, 2'b01})
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rd [15:8] <= wd;
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end
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end
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always @(posedge clk) begin
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if (we)
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mem[wa] <= wd;
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end
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endmodule
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