mirror of https://github.com/YosysHQ/yosys.git
10 lines
126 B
Verilog
10 lines
126 B
Verilog
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module tri_buf (a,b,enable);
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input a;
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output b;
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input enable;
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wire b;
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assign b = (enable) ? a : 1'bz;
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endmodule
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