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yosys/tests/arch/anlogic/dffs.ys

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Share common tests
2019-10-18 05:19:59 -05:00
read_verilog ../common/dffs.v
check ff's separately
2019-10-04 04:00:49 -05:00
design -save read
hierarchy -top dff
hierarchy - proc reorder
2019-10-18 02:06:43 -05:00
proc
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present.
2019-09-23 04:12:02 -05:00
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
check ff's separately
2019-10-04 04:00:49 -05:00
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
hierarchy -top dffe
hierarchy - proc reorder
2019-10-18 02:06:43 -05:00
proc
check ff's separately
2019-10-04 04:00:49 -05:00
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_SEQ
Replace opt_rmdff with opt_dff.
2020-07-20 16:19:51 -05:00
select -assert-none t:AL_MAP_SEQ %% t:* %D