yosys/tests/verilog/asgn_expr_not_sv_1.ys

logger -expect error "Assignments within expressions are only supported in SystemVerilog mode." 1
read_verilog <<EOF
module top;
integer x, y;
initial y = ++x;
endmodule
EOF
sv: support assignments within expressions - Add support for assignments within expressions, e.g., `x[y++] = z;` or `x = (y *= 2) - 1;`. The logic is handled entirely within the parser by injecting statements into the current procedural block. - Add support for pre-increment/decrement statements, which are behaviorally equivalent to post-increment/decrement statements. - Fix non-standard attribute position used for post-increment/decrement statements. 2023-09-05 21:19:28 -05:00			`logger -expect error "Assignments within expressions are only supported in SystemVerilog mode." 1`
			`read_verilog <<EOF`
			`module top;`
			`integer x, y;`
			`initial y = ++x;`
			`endmodule`
			`EOF`