mirror of https://github.com/YosysHQ/yosys.git
21 lines
362 B
Plaintext
21 lines
362 B
Plaintext
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read_verilog <<EOF
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module cell (input [2:12] I, output [5:-5] O);
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endmodule
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module top(input [10:0] A, output [10:0] B);
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cell my_cell(.I(A), .O(B));
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endmodule
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EOF
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write_blif tmp-bug2729.blif
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delete top
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read_blif -wideports tmp-bug2729.blif
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!rm tmp-bug2729.blif
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rename -enumerate t:cell
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dump
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cd top
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connect -assert -port _0_ I A
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connect -assert -port _0_ O B
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