mirror of https://github.com/YosysHQ/yosys.git
5 lines
147 B
Plaintext
5 lines
147 B
Plaintext
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read_verilog example.v
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synth_xilinx -top example -family xc6s
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iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I
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write_edif -pvector bra example.edif
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